hamburger-nav-icon
region-flag-icon
Search by Category
Audio
Cameras
Cases & Bags
Computers & Software
Conferencing
Content Management
Control
Displays
Furniture
Home Technology/Automation
Lighting & Studio
Mounts & Rigging
Networking & Cabling
Power
Presentation
Production
Security & Safety
Signal Management
Search by Category
EnglishFrenchGermanItalianPortugueseSpanish
 
Request Quote

Single Chip DSP Microcomputer

Model: ADSP-2191M

  • 6.25ns instruction cycle time, for up to 160 MIPS sustained performance
  • ADSP-218x family code compatible with the same easy to use algebraic syntax
  • Single-cycle instruction execution
  • Single-cycle context switch between two sets of computation and memory instructions
  • Instruction cache allows dual operand fetches in every instruction cycle
Compare
Project List
Product Info
Tech Specs
Documents
The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.

The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program.

Indirect addressing options provide addressing flexibility—premodify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering.

  • 6.25ns instruction cycle time, for up to 160 MIPS sustained performance
  • ADSP-218x family code compatible with the same easy to use algebraic syntax
  • Single-cycle instruction execution
  • Single-cycle context switch between two sets of computation and memory instructions
  • Instruction cache allows dual operand fetches in every instruction cycle
  • Unified memory space allows flexible address generation, using two independent DAG units
  • Powerful program sequencer provides zero-overhead looping and conditional instruction execution
  • Enhanced interrupt controller enables programming of interrupt priorities and nesting modes
 
Request Quote
 

Suggested Products

by Sony Professional Solutions of America